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| MCP6401/1R/1U 1 MHz, 45 A Op Amps Features * * * * * * * Low Quiescent Current: 45 A (typical) Gain Bandwidth Product: 1 MHz (typical) Rail-to-Rail Input and Output Supply Voltage Range: 1.8V to 6.0V Unity Gain Stable Extended Temperature Range: -40C to +125C No Phase Reversal Description The Microchip Technology Inc. MCP6401/1R/1U family of operational amplifiers (op amps) has low quiescent current (45 A, typical) and rail-to-rail input and output operation. This family is unity gain stable and has a gain bandwidth product of 1 MHz (typical). These devices operate with a single supply voltage as low as 1.8V. These features make the family of op amps well suited for single-supply, battery-powered applications. The MCP6401/1R/1U family is designed with Microchip's advanced CMOS process and offered in single packages. All devices are available in the extended temperature range, with a power supply range of 1.8V to 6.0V. Applications * * * * * * * Portable Equipment Battery Powered System Medical Instrumentation Data Acquisition Equipment Sensor Conditioning Supply Current Sensing Analog Active Filters Package Types MCP6401 SC70-5, SOT-23-5, VOUT 1 VSS 2 VIN+ 3 4 VIN- 5 VDD MCP6401R SOT-23-5, VOUT 1 VDD 2 VIN+ 3 4 VIN- 5 VSS Design Aids * * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes MCP6401U SOT-23-5, VIN+ 1 VSS 2 VIN- 3 4 VOUT 5 VDD Typical Application R2 D2 VIN R1 VOUT MCP6401 D1 Precision Half-Wave Rectifier (c) 2009 Microchip Technology Inc. DS22229A-page 1 MCP6401/1R/1U NOTES: DS22229A-page 2 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 1.0 1.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage And Current Limits" VDD - VSS ........................................................................7.0V Current at Input Pins .....................................................2 mA Analog Inputs (VIN+, VIN-) .......... VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short-Circuit Current .................................continuous Current at Output and Supply Pins ............................30 mA Storage Temperature ....................................-65C to +150C Maximum Junction Temperature (TJ).......................... +150C ESD protection on all pins (HBM; MM) ................ 4 kV; 400V 1.2 Specifications DC ELECTRICAL SPECIFICATIONS TABLE 1-1: Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2 and RL = 100 k to VL. (Refer to Figure 1-1). Parameters Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Ratio Input Bias Current and Impedance Input Bias Current IB -- -- -- Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Voltage Range Common Mode Rejection Ratio VCMR CMRR VSS-0.2 VSS-0.3 56 63 Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: VDD IQ 1.8 20 -- 45 6.0 70 V A IO = 0, VDD = 5.0V VCM = 0.2VDD VOL, VOH ISC VSS+20 -- -- -- 5 15 VDD-20 -- -- mV mA mA VDD = 6.0V, RL = 10 k 0.5V input overdrive VDD = 1.8V VDD = 6.0V AOL 90 110 -- dB VOUT = 0.3V to VDD-0.3V VCM = VSS -- -- 71 78 VDD+0.2 VDD+0.3 -- -- V V dB dB VDD = 1.8V, Note 1 VDD = 6.0V, Note 1 VCM = -0.2V to 2.0V, VDD = 1.8V VCM = -0.3V to 6.3V, VDD = 6.0V IOS ZCM ZDIFF -- -- -- 1.0 30 800 1.0 1013||6 1013||6 100 -- -- -- -- -- pA pA pA pA ||pF ||pF TA = +85C TA = +125C VOS VOS/TA PSRR -4.5 -- 63 -- 2.0 78 +4.5 -- -- mV VCM = VSS V/C TA= -40C to +125C, VCM = VSS dB VCM = VSS Sym Min Typ Max Units Conditions Figure 2-11 shows how VCMR changes across temperature. (c) 2009 Microchip Technology Inc. DS22229A-page 3 MCP6401/1R/1U TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. (Refer to Figure 1-1). Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 3.6 28 0.6 -- -- -- Vp-p nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz GBWP PM SR -- -- -- 1 65 0.5 -- -- -- MHz V/s G = +1 V/V Sym Min Typ Max Units Conditions TABLE 1-3: TEMPERATURE SPECIFICATIONS Parameters Sym TA TA JA JA Min -40 -65 -- -- Typ -- -- 220.7 331 Max +125 +150 -- -- Units C C C/W C/W Conditions Note 1 Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND. Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, SOT-23-5 Thermal Resistance, SC70-5 Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150C. 1.3 Test Circuits CF 6.8 pF RG 100 k VP VIN+ MCP640x VIN- VM RG 100 k (V/V) (V) (mV) CF 6.8 pF VL RF 100 k RL 100 k VOUT CL 60 pF CB1 100 nF RF 100 k VDD VDD/2 The circuit used for most DC and AC tests is shown in Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit's common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. EQUATION 1-1: V CM = ( V P + V DD 2 ) 2 V OST = V IN- - V IN+ Where: GDM = Differential Mode Gain VCM = Op Amp's Common Mode Input Voltage VOST = Op Amp's Total Input Offset Voltage V OUT = ( V DD 2 ) + ( V P - V M ) + V OST ( 1 + G DM ) G DM = R F R G CB2 1 F FIGURE 1-1: AC and DC Test Circuit for Most Specifications. DS22229A-page 4 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 0.24 Percentage of Occurences Input Offset Voltage (V) 0.21 0.18 0.15 0.12 0.09 0.06 0.03 0 -5 -4 -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) 4 5 1760 Samples VCM = VSS 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 VDD = 1.8V Representative Part TA = TA = TA = TA = +125C +85C +25C -40C 0.5 -0.3 FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. 1000 Input Offset Voltage (V) 45% Percentage of Occurences 40% 35% 30% 25% 20% 15% 10% 5% 0% -10 -8 -6 -4 -2 0 2 4 6 8 Input Offset Voltage Drift (V/C) 10 1760 Samples VCM = VSS TA = -40C to +125C 750 500 250 0 -250 -500 -750 -1000 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 6.0 0.0 0.5 1.5 Representative Part VDD = 1.8V VDD = 6.0V FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Output Voltage. 1000 Input Offset Voltage (V) 800 600 400 200 0 -200 -400 -600 -800 -0.1 Common Mode Input Voltage (V) Input Offset Voltage vs. 1000 900 800 700 600 500 400 300 200 100 0 -100 -0.5 Input Offset Voltage (V) VDD = 6.0V Representative Part TA = +125C TA = +85C TA = +25C TA = -40C Representative Part TA = TA = TA = TA = +125C +85C +25C -40C 6.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. (c) 2009 Microchip Technology Inc. DS22229A-page 5 2.3 0.1 0.3 0.9 1.1 1.3 1.9 2.1 0.7 1.5 1.7 MCP6401/1R/1U Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 1,000 Input Noise Voltage Density (nV/Hz) 90 85 CMRR, PSRR (dB) 80 75 70 65 60 55 10 50 0.1 0.1 PSRR (VDD = 1.8V to 6.0V, VCM = VSS) 100 CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V) CMRR (VDD = 1.8V, VCM = -0.2V to 2.0V) 11 100 1000 1010 100 1k Frequency (Hz) 10000 100k 100000 10k -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-7: vs. Frequency. 40 35 30 25 20 15 10 5 0 0.0 0.5 -0.5 f = 1 kHz VDD = 6.0 V Input Noise Voltage Density FIGURE 2-10: Temperature. 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -50 CMRR, PSRR vs. Ambient Common Mode Input Voltage Range Limits (V) Input Noise Voltage Density (nV/Hz) VCMR_H - VDD @ VDD = 6.0V VCMR_H - VDD @ VDD = 1.8V VCMR_L - VSS @ VDD = 1.8V VCMR_L - VSS @ VDD = 6.0V 5.5 6.0 6.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. 100 90 CMRR, PSRR (dB) 80 70 60 50 40 30 20 10 10 100 100 1k 10k 1000 10000 Frequency (Hz) 100k 1M 100000 1000000 PSRRCMRR PSRR+ Representative Part FIGURE 2-11: Common Mode Input Voltage Range Limits vs. Ambient Temperature. 10000 Input Bias, Offset Current (pA) VDD = 6.0V 1000 Input Bias Current 100 10 Input Offset Current 1 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (C) FIGURE 2-9: Frequency. CMRR, PSRR vs. FIGURE 2-12: Input Bias, Offset Current vs. Ambient Temperature. DS22229A-page 6 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 1000 Input Bias Current (pA) Open-Loop Gain (dB) TA = +125C 120 100 80 60 40 20 0 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) 1.0E-01 0 Open-Loop Gain 100 -60 Open-Loop Phase -90 -120 -150 10 VDD = 6.0V TA = +85C VDD = 6.0V -180 -210 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 100 1k 10k 100k 1M 10M Frequency (Hz) 1 0.1 1.0E+00 1 1.0E+01 10 FIGURE 2-13: Input Bias Current vs. Common Mode Input Voltage. 70 65 Quiescent Current (A/Amplifier) 60 55 50 45 40 35 30 25 20 -50 VDD = 6.0V VDD = 5.0V VDD = 1.8V FIGURE 2-16: Frequency. 150 145 140 135 130 125 120 115 110 105 100 1.5 Open-Loop Gain, Phase vs. DC Open-Loop Gain (dB) VCM = 0.2VDD RL = 10 k VSS + 0.3V < VOUT < VDD - 0.3V -25 0 25 50 75 100 Ambient Temperature (C) 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Power Supply Voltage (V) 5.5 6.0 FIGURE 2-14: Quiescent Current vs Ambient Temperature. 70 Quiescent Current (A) 60 50 40 30 20 10 0 5.0 5.5 6.0 6.5 Power Supply Voltage (V) 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 TA = +125C TA = +85C TA = +25C TA = -40C VCM = 0.2VDD FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. 150 145 VDD = 6.0V 140 135 130 125 120 VDD = 1.8V 115 110 Large Signal AOL 105 100 0.00 0.05 0.10 0.15 0.20 Output Voltage Headroom VDD - VOH or VOL-VSS (V) DC Open-Loop Gain (dB) 0.25 FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. (c) 2009 Microchip Technology Inc. DS22229A-page 7 Open-Loop Phase () -30 MCP6401/1R/1U Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 1.6 Gain Bandwidth Product (MHz) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 Ambient Temperature (C) VDD = 6.0V Phase Margin Gain Bandwidth Product 90 85 Phase Margin () 80 75 70 65 60 55 50 45 125 Output Voltage Swing (V P-P) 10 VDD = 6.0V VDD = 1.8V 1 0.1 100 100 1k 1000 10k 100k 10000 100000 Frequency (Hz) 1M 1000000 FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 1.6 Gain Bandwidth Product (MHz) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 Ambient Temperature (C) VDD = 1.8V Phase Margin Gain Bandwidth Product FIGURE 2-22: Frequency. 1000 Output Voltage Headroom (mV) 100 Output Voltage Swing vs. 90 85 75 70 65 60 55 50 45 125 Phase Margin () 80 VDD - VOH @ VDD = 1.8V VOL - VSS @ VDD = 1.8V 10 1 0.1 0.01 10 VDD - VOH @ VDD = 6.0V VOL - VSS @ VDD = 6.0V RL = 10 k 0.1 1 100 1000 Output Current (mA) 10 10000 FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 30 25 20 15 10 5 0 0.0 0.5 1.0 6.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) T A = -40C T A = +25C T A = +85C T A = +125C FIGURE 2-23: Output Voltage Headroom vs. Output Current. 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -50 -25 Output Short Circuit Current (mA) Output Voltage Headroom VDD - VOH or VOL - VSS (mV) VDD - VOH @ VDD = 6.0V VOL - VSS@ VDD = 6.0V VDD - VOH @ VDD = 1.8V VOL - VSS @ VDD = 1.8V 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-24: Output Voltage Headroom vs. Ambient Temperature. DS22229A-page 8 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 0.9 0.8 Slew Rate (V/s) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 Falling Edge, VDD = 1.8V Rising Edge, VDD = 1.8V Falling Edge, VDD = 6.0V Rising Edge, VDD = 6.0V 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (V) VDD = 6.0V G = +1 V/V Time (20 s/div) FIGURE 2-25: Temperature. Slew Rate vs. Ambient FIGURE 2-28: Pulse Response. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Large Signal Non-Inverting Output Voltage (20 mv/div) Output Voltage (V) VDD = 6.0V G = -1 V/V VDD = 6.0V G = +1 V/V Time (2 s/div) Time (20 s/div) FIGURE 2-26: Pulse Response. Small Signal Non-Inverting FIGURE 2-29: Response. 7.0 Large Signal Inverting Pulse Output Voltage (20 mv/div) Input, Output Voltages (V) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 VDD = 6.0V G = +2 V/V VIN VOUT VDD = 6.0V G = -1 V/V Time (2 s/div) Time (0.1 ms/div) FIGURE 2-27: Response. Small Signal Inverting Pulse FIGURE 2-30: The MCP6401/1R/1U Shows No Phase Reversal. (c) 2009 Microchip Technology Inc. DS22229A-page 9 MCP6401/1R/1U Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 60 pF. 10000 Closed Loop Output Impedance () 1m 1.E-03 1.E-04 100 1.E-05 10 1.E-06 1 -IIN (A) 1.E-07 100n 1.E-08 10n 1.E-09 1n 1.E-10 100p 1.E-11 10p 1.0E+06 1000 100 GN: 101 V/V 11 V/V 1 V/V 10 TA TA TA TA = -40C = +25C = +85C = +125C 1 1.0E+01 10 1.0E+02 100 1.0E+04 1k 10k Frequency (Hz) 1.0E+03 1.0E+05 100k 1M 1.E-12 1p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VIN (V) FIGURE 2-31: Closed Loop Output Impedance vs. Frequency. FIGURE 2-32: Measured Input Current vs. Input Voltage (below VSS). DS22229A-page 10 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP6401 SC70-5, SOT-23-5 1 2 3 4 5 PIN FUNCTION TABLE MCP6401R SOT-23-5 1 5 3 4 2 MCP6401U SOT-23-5 4 2 1 3 5 Symbol VOUT VSS VIN+ VIN- VDD Analog Output Negative Power Supply Non-inverting Input Inverting Input Positive Power Supply Description 3.1 Analog Output (VOUT) 3.3 Power Supply Pin (VDD, VSS) The output pin is low-impedance voltage source. 3.2 Analog Inputs (VIN+, VIN-) The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. The positive power supply (VDD) is 1.8V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. (c) 2009 Microchip Technology Inc. DS22229A-page 11 MCP6401/1R/1U NOTES: DS22229A-page 12 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 4.0 APPLICATION INFORMATION VDD D1 V1 R1 V2 R2 R3 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > MCP640x D2 The MCP6401/1R/1U family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power, high precision applications. 4.1 4.1.1 Rail-to-Rail Input PHASE REVERSAL The MCP6401/1R/1U op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-30 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltage that go too far above VDD; their breakdown voltage is high enough to allow normal operation and low enough to bypass ESD events within the specified limits. FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistors R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC currents into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS). (See Figure 2-32). VDD Bond Pad 4.1.3 NORMAL OPERATION VIN+ Bond Pad Input Stage Bond VIN- Pad VSS Bond Pad The input stage of the MCP6401/1R/1U op amps uses two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. (See Figure 2-11). The input offset voltage is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the input stages occurs when VCM is near VDD - 1.1V (See Figures 2-3 and 2-4). For the best distortion performance and gain linearity, with non-inverting gains, avoid this region of operation. FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the voltages and currents at the VIN+ and VIN- pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. 4.2 Rail-to-Rail Output The output voltage range of the MCP6401/1R/1U op amps is VSS + 20 mV (minimum) and VDD - 20 mV (maximum) when RL = 10 k is connected to VDD/2 and VDD = 6.0V. Refer to Figures 2-23 and 2-24 for more information. (c) 2009 Microchip Technology Inc. DS22229A-page 13 MCP6401/1R/1U 4.3 Capacitive Loads 4.4 Supply Bypass Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1 V/V) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1 V/V), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load. With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.5 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow; which is greater than the MCP6401/1R/1U family's bias current at +25C (1.0 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-5. - MCP640x VIN + RISO VOUT CL FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 10000 () VDD = 6.0 V RL = 10 k Guard Ring VIN- VIN+ VSS FIGURE 4-5: for Inverting Gain. 1. Example Guard Ring Layout Recommended R ISO 1000 100 10 GN: 1 V/V 2 V/V 5 V/V 1 10p 100p 1n 10n 0.1 1 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; CL/GN (F) 2. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6401/1R/1U SPICE macro model are very helpful. Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. DS22229A-page 14 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 4.6 4.6.1 Application Circuits PRECISION HALF-WAVE RECTIFIER 4.6.2 BATTERY CURRENT SENSING The precision half-wave rectifier, which is also known as a super diode, is a configuration obtained with an operational amplifier in order to have a circuit behaving like an ideal diode and rectifier. It effectively cancels the forward voltage drop of the diode so that very low level signals can still be rectified with minimal error. This can be useful for high-precision signal processing. The MCP6401/1R/1U op amps have high input impedance, low input bias current and rail-to-rail input/output, which makes this device suitable for precision rectifier applications. Figure 4-6 shows a precision half-wave rectifier and its transfer characteristic. The rectifier's input impedance is determined by the input resistor R1. To avoid loading effect, it must be driven from a low impedance source. When VIN is greater than zero, D1 is OFF and D2 is ON, VOUT is zero. When VIN is less than zero, D1 is ON and D2 is OFF, and VOUT is the VIN with an amplification of -R2/R1. The rectifier circuit shown in Figure 4-6 has the benefit that the op amp never goes in saturation, so the only thing affecting its frequency response is the amplification and the gain bandwidth product. . The MCP6401/1R/1U op amps' Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current sensing applications. The low quiescent current (45 A, typical) helps prolong battery life, and the rail-to-rail output supports detection of low currents. Figure 4-7 shows a high side battery current sensor circuit. The 10 resistor is sized to minimize power losses. The battery current (IDD) through the 10 resistor causes its top terminal to be more negative than the bottom terminal. This keeps the common mode input voltage of the op amp below VDD, which is within its allowed range. The output of the op amp will also be below VDD, which is within its Maximum Output Voltage Swing specification. IDD 1.8V to 6.0V 10 100 k VDD MCP6401 1 M V DD - V OUT I DD = ----------------------------------------( 10 V/V ) ( 10 ) To load VOUT R2 D2 VIN R1 VOUT MCP6401 D1 FIGURE 4-7: 4.6.3 Supply Current Sensing. INSTRUMENTATION AMPLIFIER The MCP6401/1R/1U op amps are well suited for conditioning sensor signals in battery-powered applications. Figure 4-8 shows a two op amp instrumentation amplifier, using the MCP6401, that works well for applications requiring rejection of common mode noise at higher gains. The reference voltage (VREF) is supplied by a low impedance source. In single supply applications, VREF is typically VDD/2. RG VREF R1 R2 R2 R1 VOUT Precision Half-Wave Rectifier VOUT -R2/R1 V2 MCP6401 VIN Transfer Characteristic V1 MCP6401 FIGURE 4-6: Rectifier. Precision Half-Wave R 1 2R 1 V OUT = ( V 1 - V 2 ) 1 + ----- + -------- + V REF R2 RG FIGURE 4-8: Two Op Amp Instrumentation Amplifier. (c) 2009 Microchip Technology Inc. DS22229A-page 15 MCP6401/1R/1U NOTES: DS22229A-page 16 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 5.0 DESIGN AIDS 5.4 Microchip provides the basic design tools needed for the MCP6401/1R/1U family of op amps. Microchip Advanced Part Selector (MAPS) 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6401/1R/ 1U op amp is available on the Microchip web site at www.microchip.com. The model was written and tested in official Orcad (Cadence) owned PSPICE. For the other simulators, it may require translation. The model covers a wide aspect of the op amp's electrical specifications. Not only does the model cover voltage, current, and resistance of the op amp, but it also covers the temperature and noise effects on the behavior of the op amp. The model has not been verified outside of the specification range listed in the op amp data sheet. The model behaviors under these conditions cannot be guaranteed that it will match the actual op amp performance. Moreover, the model is intended to be an initial design tool. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts. 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Some boards that are especially useful are: * * * * * * * MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV 5.2 FilterLab(R) Software Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 MindiTM Circuit Designer & Simulator Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. (c) 2009 Microchip Technology Inc. DS22229A-page 17 MCP6401/1R/1U 5.6 Application Notes The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1177: "Op Amp Precision Design: DC Errors", DS01177 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 * AN1297: "Microchip's Op Amp SPICE Macro Models", DS01297 These application notes and others are listed in the design guide: * "Signal Chain Design Guide", DS21825 DS22229A-page 18 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SC70 (MCP6401 only) Example: XXNN BL25 5-Lead SOT-23 Example: Part Number Code NLNN NMNN NPNN XXNN MCP6401T-E/OT MCP6401RT-E/OT MCP6401UT-E/OT NL25 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. DS22229A-page 19 MCP6401/1R/1U /HDG 3ODVWLF 6PDOO 2XWOLQH 7UDQVLVWRU /7 >6& 1RWH @ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D b 3 2 1 E1 E 4 e e 5 A A2 c A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 1 H $ $ $ ( ( ' / F E %6& 0,1 0,//,0(7(56 120 0$; L 1RWHV 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS22229A-page 20 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ (c) 2009 Microchip Technology Inc. DS22229A-page 21 MCP6401/1R/1U /HDG 3ODVWLF 6PDOO 2XWOLQH 7UDQVLVWRU 27 >627 1RWH @ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ b N E E1 1 e 2 3 e1 D A A2 c A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV /HDG 3LWFK 2XWVLGH /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H H $ $ $ ( ( ' / / I F %6& %6& 0,1 0,//,0(7(56 120 0$; /HDG :LGWK E 1RWHV 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS22229A-page 22 (c) 2009 Microchip Technology Inc. MCP6401/1R/1U/2 APPENDIX A: REVISION HISTORY Revision A (December 2009) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS22229A-page 23 MCP6401/1R/1U/2 NOTES: DS22229A-page 24 (c) 2009 Microchip Technology Inc. MCP6401/IR/1U PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Single Op Amp (Tape and Reel) (SC70-5, SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) MCP6401T-E/LT: MCP6401T-E/OT: MCP6401RT-E/OT: MCP6401UT-E/OT: Device: MCP6401T: MCP6401RT: MCP6401UT: c) d) Tape and Reel, 5LD SC70 pkg Tape and Reel, 5LD SOT-23 pkg Tape and Reel, 5LD SOT-23 pkg Tape and Reel, 5LD SOT-23 pkg Temperature Range: E = -40C to +125C Package: LT = Plastic Package (SC70), 5-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead (c) 2009 Microchip Technology Inc. DS22229A-page 25 MCP6401/IR/1U NOTES: DS22229A-page 26 (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. 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